Conventional optical projection lithography has been the standard silicon patterning technology in semiconductor manufacturing processes, for example, in the fabrication of integrated circuits (ICs). An optical projection lithography process can include a patterned mask with a semiconductor circuit layout pattern which is used to image the pattern onto a photosensitive layer, for example photoresist. The photoresist covers a layer to be patterned such as a polysilicon layer which is part of a semiconductor wafer. Layouts used to create such masks are typically generated using computer-aided design (CAD) programs, sometimes called electronic design automation (EDA).
One goal in IC fabrication is to faithfully reproduce the original circuit design or layout on the wafer, specifically into the layer to be patterned, using the designed mask. Another goal is to use as much of the wafer real estate as possible. As the size of an IC is reduced and its density increases, however, the critical dimension of its corresponding mask approaches the resolution limit of the optical exposure tool. Critical dimension (i.e., CD), for purposes of this disclosure, is the smallest physical dimension printable on a wafer below which the feature size is not reliably reproducible. For example, transistor matching requirements for advanced technology nodes, such as less than 1.0 μm, require exquisite CD control, beyond the capability of current lithography and etch tools and processes. An important component of variation is matching between transistor gates in the interior of an array of active gates, e.g., over the same active region, and those on the end of the array. For example, for the 45 nm technology node, the printed transistor gates at the ends of the gate array might vary from their designed size by an amount which is 2 to 3 times the variation of the transistor gates at the interior of the array.
Features such as polysilicon transistor gates can be formed with a process which uses a single mask exposure of the photosensitive layer and a single etch using the patterned photosensitive layer to etch an underlying layer such as a polysilicon layer to form the polysilicon transistor gates. In this process, the layer to be etched, for example, the blanket polysilicon layer; is formed, then the photosensitive layer is formed over the polysilicon layer. A light source is patterned by the mask, the patterned light source exposes the photoresist, then the exposed photoresist (positive resist) or the unexposed photoresist (negative resist) is removed to pattern the photoresist. The polysilicon layer is then etched using the patterned photoresist as a pattern. Subsequently, the patterned photoresist is removed and wafer processing can continue.
In semiconductor device design, an extension of a transistor gate past the active region is an important consideration. Without sufficient extension of the transistor gate past the end of the active region, line end shortening and corner rounding can pull the end of the transistor gate back to such an extent that device leakage can occur, severely compromising the device performance. In some cases, a device can be rendered inoperable. U.S. Pat. Publication 2009/0169832, which is incorporated by reference herein in its entirety, describes problems associated with line end shortening.
A process which provides a more faithful reproduction of a circuit layout within a resist layer and, therefore, within a layer underlying the resist layer, would be desirable.